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1 lt1339 sn1339 1339fas high power synchronous dc/dc controller descriptio n u features the lt ? 1339 is a high power synchronous current mode switching regulator controller. the ic drives dual n-channel mosfets to create a single ic solution for high power dc/dc converters in applications up to 60v. the lt1339 incorporates programmable average current limiting, allowing accurate limiting of dc load current independent of inductor ripple current. the ic also incor- porates user-adjustable slope compensation for minimi- zation of magnetics at duty cycles up to 90%. the lt1339 timing oscillator operating frequency is pro- grammable and can be synchronized up to 150khz. mini- mum off-time operation provides main switch protection. the ic also incorporates a soft start feature that is gated by both shutdown and undervoltage lockout conditions. an output phase reversal pin allows flexibility in configu- ration of converter types, including inverting and negative topologies. n high voltage: operation up to 60v n high current: dual n-channel synchronous drive handles up to 10,000pf gate capacitance n programmable average load current limiting n 5v reference output with 10ma external loading capability n programmable fixed frequency synchronizable current mode operation up to 150khz n undervoltage lockout with hysteresis n programmable start inhibit for power supply sequencing and protection n adaptive nonoverlapping gate drive prevents shoot-through n 48v telecom power supplies n personal computers and peripherals n distributed power converters n industrial control systems n lead-acid battery backup systems n automotive and heavy equipment applicatio n s u typical applicatio n u , ltc and lt are registered trademarks of linear technology corporation. 28v to 5v 20a buck converter sync v boost 5v ref tg ct ts sl/adj 12v in i avg bg ss pgnd v c phase sgnd run/shdn v fb sense + v ref sense dbst in5819 12v v in 28v c in 1500 f 63v 3 irl3803 irl3103d2 2 l1 10 h v out 5v at 20a r fb2 1k r fb1 3k lt1339 + cbst 1 f + c 12vin 47 f + c out 2200 f 6.3v 2 + d2 mbr0520 d1 mbr0520 r run 100k r s 0.005 r ct 10k c ct 2200pf c avg 2200pf c ss , 1 f c vc , 1nf r vc , 10k c ref 0.1 f 1339 ta03 l1 = ctx02-13400-x2 c 5vref 1 f + + 28v to 5v efficiency output current (a) 0 efficiency (%) 20 1339 ta03a 5 10 15 100 90 80 70 60 50
2 lt1339 sn1339 1339fas a u g w a w u w a r b s o lu t exi t i s 12v in = v boost = 12v, v c = 2v, ts = 0v, v fb = v ref = 1.25v, c tg = c bg = 3000pf, t a = 25 c unless otherwise noted. e lectr ic al c c hara terist ics symbol parameter conditions min typ max units supply and protection i 12vin dc active supply current (note 2) l 14 20 ma dc standby supply current v run/shdn < 0.5v l 150 250 m a i boost dc active supply current (note 2) 2.2 ma dc standby supply current v run/shdn < 0.5v 0 m a v run/shdn shutdown rising threshold l 1.15 1.25 1.35 v v sshyst shutdown threshold hysteresis 25 mv i ss soft start charge current l 4814 m a v uvlo undervoltage lockout threshold - falling l 8.20 9.00 9.75 v undervoltage lockout threshold - rising l 9.35 9.95 v undervoltage lockout hysteresis l 200 350 mv 5v reference v ref5 5v reference voltage line, load and temperature l 4.75 5.00 5.25 v 5v reference line regulation 10v 12v in 15v l 3 5 mv/v i ref5 5v reference load range - dc l 10 ma pulse l 20 ma 5v reference load regulation 0 i ref5 20ma l C 1.25 C 2 v/a i sc 5v reference short-circuit current 45 ma supply voltages power supply voltage (12v in )...............C 0.3v to 20v topside supply voltage (v boost ) v ts C 0.3v to v ts + 20v (v max = 75v) topside reference pin voltage (ts) ......C 0.3v to 60v input voltages sense amplifier input common mode ...C 0.3v to 60v run/shdn pin voltage ...................... C 0.3v to 12v in all other inputs ....................................... C 0.3v to 7v maximum currents 5v reference output current............................ 65ma maximum temperatures operating ambient temperature range lt1339c ............................................ 0 c to 70 c lt1339i ......................................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c (note 1) order part number lt1339cn lt1339csw lt1339in lt1339isw top view n package 20-lead pdip sw package 20-lead plastic so wide 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 sync 5v ref ct sl/adj i avg ss v c sgnd v fb v ref v boost tg ts 12v in bg pgnd phase run/shdn sense sense + wu u package / o rder i for atio t jmax = 125 c, q ja = 70 c/w (n) t jmax = 125 c, q ja = 85 c/w (sw) consult factory for military grade parts.
3 lt1339 sn1339 1339fas 12v in = v boost = 12v, v c = 2v, ts = 0v, v fb = v ref = 1.25v, c tg = c bg = 3000pf, t a = 25 c unless otherwise noted. e lectr ic al c c hara terist ics symbol parameter conditions min typ max units error amplifier v fb error amplifier reference voltage measured at feedback pin 1.242 1.250 1.258 v l 1.235 1.250 1.265 v i fb feedback input current v fb = v ref l 0.1 0.5 1.0 m a g m error amplifier transconductance l 1200 2000 3200 m mho a v error amplifier voltage gain l 1500 3000 v/v i vc error amplifier source current l 200 275 m a error amplifier sink current v fb C v ref = 500mv l 280 400 m a v vc absolute v c clamp voltage measured at v c pin 3.5 v v sense peak current limit threshold measured at sense inputs l 170 190 mv average current limit threshold (note 4) measured at sense inputs l 110 120 130 mv v iavg average current limit threshold measured at i avg pin 2.5 v current sense amplifier a v amplifier dc gain measured at i avg pin 15 v/v v os amplifier input offset voltage 2v < v cmsense < 60v, l 0.1 mv sense + C sense C = 5mv i b input bias current sink (v cmsense > 5v) l 45 75 m a source (v cmsense = 0v) l 700 1200 m a oscillator f o operating frequency, free run l 150 khz frequency programming error (note 3) f o 150khz l C5 5 % i ct timing capacitor discharge current lt1339c l 2.20 2.50 2.75 ma lt1339i l 2.10 2.50 2.75 ma v sync sync input threshold rising edge l 0.8 2.0 v f sync sync frequency range f sync 150khz l f o 1.4f o output drivers v tg,bg undervoltage output clamp 12v in 8v l 0.4 0.7 v standby mode output clamp v run < 0.5v l 0.1 v v tg top gate on voltage l 11.0 11.9 12.0 v top gate off voltage l 0.4 0.7 v t tgr top gate rise time l 130 200 ns t tgf top gate fall time l 60 140 ns v bg bottom gate on voltage l 11.0 11.9 12.0 v bottom gate off voltage l 0.4 0.7 v t bgr bottom gate rise time l 70 200 ns t bgf bottom gate fall time l 60 140 ns note 2: supply current specification does not include external fet gate charge currents. actual supply currents will be higher and vary with operating frequency, operating voltages and the type of external fets used. see application information section. note 3: test condition: r ct = 16.9k, c ct = 1000pf. note 4: test condition: v cmsense = 10v. the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.
4 lt1339 sn1339 1339fas typical perfor m a n ce characteristics uw temperature ( c) ?0 boost supply current (ma) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 25 75 1339 g01 ?5 0 50 100 125 boost supply current vs temperature temperature ( c) ?0 5v reference short-circuit current (ma) 60 55 50 45 40 35 30 25 75 1339 g03 ?5 0 50 100 125 temperature ( c) ?0 i 12vin supply current (ma) 100 1339 g02 050 18 17 16 15 14 13 12 11 10 25 25 75 125 12v in supply current vs temperature 5v reference short-circuit current vs temperature i 12vin shutdown current vs temperature reference voltage vs temperature 5v reference voltage vs temperature temperature ( c) ?0 i 12vin shutdown current ( a) 190 180 170 160 150 140 130 25 75 1339 g04 ?5 0 50 100 125 temperature ( c) ?0 reference voltage (v) 1.252 1.251 1.250 1.249 1.248 1.247 1.246 25 75 1339 g05 ?5 0 50 100 125 temperature ( c) ?0 5v reference voltage (v) 5.01 5.00 4.99 4.98 25 75 1339 g06 ?5 0 50 100 125 temperature ( c) ?0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 25 75 1339 g07 ?5 0 50 100 125 error amplifier voltage gain (kv/v) temperature ( c) ?0 error amplifier transconductance (m ) 2.6 2.4 2.2 2.0 1.8 1.6 1.4 25 75 1339 g08 ?5 0 50 100 125 temperature ( c) ?0 error amplifier source current ( a) 350 325 300 275 250 225 200 25 75 1339 g09 ?5 0 50 100 125 error amplifier voltage gain vs temperature error amplifier transconductance vs temperature error amplifier maximum source current vs temperature
5 lt1339 sn1339 1339fas typical perfor m a n ce characteristics uw temperature ( c) ?0 soft start charge current ( a) 9 8 7 6 25 75 1339 g10 ?5 0 50 100 125 soft start charge current vs temperature run/shdn threshold hysteresis vs temperature temperature ( c) ?0 run/shdn threshold hysteresis (mv) 26 25 24 23 22 21 20 25 75 1339 g12 ?5 0 50 100 125 temperature ( c) ?0 run/shdn rising threshold (v) 1.26 1.25 1.24 1.23 1.22 1.21 1.20 25 75 1339 g11 ?5 0 50 100 125 run/shdn rising threshold vs temperature bottom gate capacitance (pf) 1000 bottom gate transition times (ns) 10000 1339 g13 2500 5000 7500 160 140 120 100 80 60 40 20 0 fall time rise time t a = 25 c bottom gate transition times vs bottom gate capacitance top gate transition times vs top gate capacitance top gate capacitance (pf) 1000 top gate transition times (ns) 10000 1339 g14 2500 5000 7500 300 250 200 150 100 50 0 fall time rise time t a = 25 c v sense(cm) (v) 0 v sense (mv) 45 60 1339 g15 1 2 3 160 150 140 130 120 110 100 90 80 upper limit full operating temperature range typical lower limit average current limit threshold sense voltage tolerance vs common mode voltage 12v in supply current vs supply voltage 12v in supply voltage (v) 10 12v in supply current (ma ) 15 14 1339 g16 11 12 13 30 28 26 24 22 20 18 16 14 c bg = 1000pf c bg = 3300pf c bg = 4700pf c bg = 10000pf f o = 100khz t a = 25 c boost supply current vs 12v in supply voltage 12v in supply voltage (v) 10 boost supply current (ma ) 15 14 1339 g17 11 12 13 18 16 14 12 10 8 6 4 2 c tg = 1000pf c tg = 3300pf c tg = 4700pf c tg = 10000pf f o = 100khz t a = 25 c
6 lt1339 sn1339 1339fas temperature ( c) ?0 operating frequency (normalized) 1.01 1.00 0.99 0.98 25 75 1339 g24 ?5 0 50 100 125 typical perfor m a n ce characteristics uw temperature ( c) ?0 i b(sink) ( a) 60 55 50 45 40 35 30 25 75 1339 g20 ?5 0 50 100 125 v cmsense = 10v sense amplifier input bias current (sink) vs temperature uvlo thresholds vs temperature sense amplifier input bias current (source) vs temperature run/shdn input voltage (v) 0 run/shdn input current (na ) 2.5 2.0 1339 g22 0.5 1.0 1.5 (1.25) 800 700 600 500 400 300 200 100 0 .................................................................. typical upper limit full operating temperature range lower limit run/shdn input current vs pin voltage operating frequency (normalized) vs temperature temperature ( c) ?0 v 12vin (v) 100 1339 g18 050 10.00 9.75 9.50 9.25 9.00 8.75 8.50 8.25 8.00 25 25 75 125 rising falling run/shdn supply voltage (v) 0 run/shdn input current ( a) 600 450 300 150 0 2468 1339 g23 10 12 upper limit lower limit typical full operating temperature range run/shdn input current vs pin voltage maximum duty cycle vs r ct r ct (k ) 1246 maximum duty cycle (%) 100 90 80 70 60 50 40 30 20 10 0 10 20 40 60 100 1339 g21 i dischg = 2.1ma i dischg = 2.75ma full operating temperature range temperature ( c) ?0 i b(source) ( a) 100 1339 g19 050 1200 1100 1000 900 800 700 600 500 400 25 25 75 125 v cmsense = 0v
7 lt1339 sn1339 1339fas sync (pin 1): oscillator synchronization pin with ttl- level compatible input. input drives internal rising edge triggered one-shot; sync signal on/off times should be 3 1 m s (10% to 90% dc at 100khz). does not contain internal pull-up. connect to sgnd if not used. 5v ref (pin 2): 5v output reference. allows connection of external loads up to 10ma dc. (reference is not available in shutdown.) typically bypassed with 1 m f capacitor to sgnd. ct (pin 3): oscillator timing pin. connect a capacitor (c ct ) to ground and a pull-up resistor (r ct ) to the 5v ref supply. typical values are ct = 1000pf and 10k r ct 30k. sl/adj (pin 4): slope compensation adjustment. allows increased slope compensation for certain high duty cycle applications. resistive loading of the pin increases effective slope compensation. a resistor divider from the 5v ref pin can tailor the onset of addi- tional slope compensation to specific regions in each switch cycle. pin can be floated or connected to 5v ref if no additional slope compensation is required. (see applications information section for slope compensa- tion details.) i avg (pin 5): average current limit integration. fre- quency response characteristic is set using the 50k w output impedance and external capacitor to ground. averaging roll-off typically set at 1 to 2 orders of magni- tude under switching frequency. (typical capacitor value ~1000pf for f o = 100khz.) shorting this pin to sgnd will disable the average current limit function. ss (pin 6): soft start. generates ramping threshold for regulator current limit during start-up and after uvlo event by sourcing about 8 m a into an external capacitor. v c (pin 7): error amplifier output. rc load creates dominant compensation in power supply regulation feed- back loop to provide optimum transient response. (see applications information section for compensation de- tails.) sgnd (pin 8): small-signal ground. connect to negative terminal of c out . v fb (pin 9): error amplifier inverting input. used as voltage feedback input node for regulator loop. pin sources about 0.5 m a dc bias current to protect from an open feedback path condition. pi n fu n ctio n s uuu v ref (pin 10): bandgap generated voltage reference decoupling. connect a capacitor to signal ground. (typi- cal capacitor value ~0.1 m f.) sense + (pin 11): current sense amplifier inverting input. connect to most positive (dc) terminal of current sense resistor. sense C (pin 12): current sense amplifier noninverting input. connect to most negative (dc) terminal of current sense resistor. run/shdn (pin 13): precision referenced shutdown. can be used as logic level input for shutdown control or as an analog monitor for input supply undervoltage protection, etc. ic is enabled when run/shdn pin rising edge exceeds 1.25v. about 25mv of hysteresis helps assure stable mode switching. all internal functions are disabled in shutdown mode. if this function is not desired, connect run/shdn to 12v in (typically through a 100k resistor). see applications information section. phase (pin 14): output driver phase control. if pin 14 is not connected (floating), the topside driver operates the main switch, with the bottom side driver operating the synchronous switch. shorting pin 14 to ground reverses the roles of the output drivers. phase is typi- cally shorted to ground for inverting and boost configu- rations. positive buck configuration requires the phase pin to float. see applications information section. pgnd (pin 15): power ground. references the bottom side output switch and internal driver control circuits. connect with low impedance trace to v in decoupling capacitor negative (ground) terminal. bg (pin 16): bottom side output driver. connects to gate of bottom side external power fet. 12v in (pin 17): 12v power supply input. bypass with at least 1 m f to pgnd. ts (pin 18): boost output driver reference. typically connects to source of topside external power fet and inductive switch node. tg (pin 19): topside (boost) output driver. connects to gate of topside external power fet. v boost (pin 20): topside power supply. bootstrapped via 1 m f capacitor tied to switch node (pin 18) and schottky diode connected to the 12v in supply.
8 lt1339 sn1339 1339fas operatio n u basic control loop the lt1339 uses a constant frequency, current mode synchronous architecture. the timing of the ic is provided through an internal oscillator circuit, which can be syn- chronized to an external clock, programmable to operate at frequencies up to 150khz. the oscillator creates a modified sawtooth wave at its timing node (ct) with a slow charge, rapid discharge characteristic. during typical positive buck operation, the main switch mosfet is enabled at the start of each oscillator cycle. the main switch stays enabled until the current through the switched inductor, sensed via the voltage across a series (refer to functional block diagram) sense resistor (r sense ), is sufficient to trip the current comparator (ic1) and, in turn, reset the rs latch. when the rs latch resets, the main switch is disabled, and the synchronous switch mosfet is enabled. shoot-through prevention logic prohibits enabling of the synchronous switch until the main switch is fully disabled. if the current comparator threshold is not obtained throughout the entire oscillator charge period, the rs latch is bypassed and the main switch is disabled during the oscillator discharge time. this minimum off time assures ad- equate charging of the bootstrap supply, protects the main switch, and is typically about 1 m s. + + 1.25v soft start 8 a ss i avg v c + + ea 1.25v 5v reference v fb 0.5 a 15 current sense amp ic1 sr q osc sl/adj nonoverlapping switch logic uvlo circuit ct tg v boost phase 12v in ts bg sense + v in 5v ref main switch sync switch sense r sense v out 1339 ?bd circuit enable + 2.5v pgnd sgnd + one shot 50k average current limit run/shdn 5v ref v ref sync uu w fu ctio al block diagra
9 lt1339 sn1339 1339fas operatio n u (refer to functional block diagram) the current comparator trip threshold is set on the v c pin, which is the output of a transconductance amplifier, or error amplifier (ea). the error amplifier integrates the difference between a feedback voltage (on the v fb pin) and an internal bandgap generated reference voltage of 1.25v, forming a signal that represents required load current. if the supplied current is insufficient for a given load, the output will droop, thus reducing the feedback voltage. the error amplifier forces current out of the v c pin, increasing the current comparator threshold. thus, the circuit will servo until the provided current is equal to the required load and the average output voltage is at the value programmed by the feedback resistors. average current limit the output of the sense amplifier is monitored by a single pole integrator comprised of an external capacitor on the i avg pin and an internal impedance of approximately 50k w . if this averaged value signal exceeds a level corre- sponding to 120mv across the external sense resistor, the current comparator threshold is clamped and cannot continue to rise in response to the error amplifier. thus, if average load current requirements exceed 120mv/r sense , the supply will current limit and the output voltage will fall out of regulation. the average current limit circuit moni- tors the sense amplifier output without slope compensa- tion or ripple current contributions, therefore the average load current limit threshold is unaffected by duty cycle. undervoltage lockout the lt1339 employs an undervoltage lockout circuit (uvlo) that monitors the 12v supply rail. this circuit disables the output drive capability of the lt1339 if the 12v supply drops below about 9v. unstable mode switching is prevented through 350mv of uvlo threshold hysteresis. adaptive nonoverlapping output stage the fet driver output stage implements adaptive nonoverlapping control. this circuitry maintains dead time independent of the type, size or operating conditions of the switch elements. the control circuit monitors the output gate drive signals, insuring that the switch gate (being disabled) is fully discharged before enabling the other switch driver. shutdown the lt1339 can be put into low current shutdown mode by pulling the run/shdn pin low, disabling all circuit functions. the shutdown threshold is a bandgap referred voltage of 1.25v typical. use of a precision threshold on the shutdown circuit enables use of this pin for undervolt- age protection of the v in supply and/or power supply sequencing. soft start the lt1339 incorporates a soft start function that oper- ates by slowly increasing the internal current limit. this limit is controlled by clamping the v c node to a low voltage that climbs with time as an external capacitor on the ss pin is charged with about 8 m a. this forces a graceful climb of output current capability, and thus a graceful increase in output voltage until steady-state regulation is achieved. the soft start timing capacitor is clamped to ground during shutdown and during undervoltage lockout, yield- ing a graceful output recovery from either condition. 5v internal reference power for the oscillator timing elements and most other internal lt1339 circuits is derived from an internal 5v reference, accessible at the 5v ref pin. this supply pin can be loaded with up to 10ma dc (20ma pulsed) for convenient biasing of local elements such as control logic, etc. slope compensation for duty cycles greater than 50%, slope compensation is required to prevent current mode duty cycle instability in the regulator control loop. the lt1339 employs internal slope compensation that is adequate for most applica- tions. however, if additional slope compensation is desired, it is available through the sl/adj pin. excessive slope compensation will cause reduction in maximum load current capability and therefore is not desirable.
10 lt1339 sn1339 1339fas applicatio n s i n for m atio n wu u u r sense selection for output current r sense generates a voltage that is proportional to the inductor current for use by the lt1339 current sense amplifier. the value of r sense is based on the required load current. the average current limit function has a typical threshold of 120mv/r sense , or: r sense = 120mv/i limit operation with v sense common mode voltage below 4.5v may slightly degrade current limit accuracy. see average current limit threshold tolerance vs common mode voltage curve in the typical performance characteristics section for more information. output voltage programming output voltage is programmed through a resistor feed- back network to v fb (pin 9) on the lt1339. this pin is the inverting input of the error amplifier, which is internally referenced to 1.25v. the divider is ratioed to provide 1.25v at the v fb pin when the output is at its desired value. the output voltage is thus set following the relation: v out = 1.25(1 + r2/r1) when an external resistor divider is connected to the output as shown in figure 1. the minimum off-time of the pwm controller. this limits maximum duty cycle (dc max ) to: dc max = 1 C (t disch )(f o ) this relation corresponds to the minimum value of the timing resistor (r ct ), which can be determined according to the following relation (r ct vs dc max graph appears in the typical performance characteristics section): r ct(min) ? [(0.8)(10 C3 )(1 C dc max )] C1 values for r ct > 15k yield maximum duty cycles above 90%. given a timing resistor value, the value of the timing capacitor (c ct ) can then be determined for desired oper- ating frequency (f o ) using the relation: c f r r ct o ct ct ? () - () ? ? ? () + () ? ? ? - () - - 1 100 10 185 175 2 5 10 3 375 9 3 / /. . ../ a plot of operating frequency vs r ct and c ct is shown in figure 2. typical 100khz operational values are c ct = 1000pf and r ct = 16.9k. r1 r2 v out 1339 ?f01 v fb sgnd lt1339 9 8 figure 1. programming lt1339 output voltage if high value feedback resistors are used, the input bias current of the v fb pin (1 m a maximum) could cause a slight increase in output voltage. a thevenin resistance at the v fb pin of <5k is recommended. oscillator components r ct and c ct the lt1339 oscillator creates a modified sawtooth wave at its timing node (ct) with a slow charge, rapid discharge characteristic. the rapid discharge time corresponds to figure 2. oscillator frequency vs r ct , c ct average current limit the average current limit function is implemented using an external capacitor (c avg ) connected from i avg to sgnd that forms a single pole integrator with the 50k w output timing resistor (k ) 0 oscillator frequency (khz) 15 25 lt1339 ?f02 510 20 160 140 120 100 80 60 40 20 0 30 c ct = 3.3nf c ct = 2.2nf c ct = 1.5nf c ct = 1.0nf
11 lt1339 sn1339 1339fas applicatio n s i n for m atio n wu u u impedance of the i avg pin. the integrator corner fre- quency is typically set 1 to 2 orders of magnitude below the oscillator frequency and follows the relation: f C3db = (3.2)(10 C6 )/c avg the average current limit function can be disabled by shorting the i avg pin directly to sgnd. soft start programming the current control pin (v c ) limits sensed inductor current to zero at voltages less than a transistor v be , to full average current limit at v c = v be + 1.8v. this generates a 1.8v full regulation range for average load current. an internal voltage clamp forces the v c pin to a v be C 100mv above the ss pin voltage. this 100mv dead zone assures 0% duty cycle operation at the start of the soft start cycle, or when the soft start pin is pulled to ground. given the typical soft start current of 8 m a and a soft start timing capacitor c ss , the start-up delay time to full available average current will be: t ss = (1.5)(10 5 )(c ss ) boost supply the v boost supply is bootstrapped via an external capaci- tor. this supply provides gate drive to the topside switch fet. the bootstrap capacitor is charged from 12v in through a diode when the switch node is pulled low. the diode reverse breakdown voltage must be greater than v in + 12v in . the bootstrap capacitor should be at least 100 times greater than the total input capacitance of the topside fet. a capacitor in the range of 0.1 m f to 1 m f is generally adequate for most applications. shutdown function input undervoltage detect and threshold hysteresis the lt1339 run/shdn pin uses a bandgap generated reference threshold of about 1.25v. this precision thresh- old allows use of the run/shdn pin for both logic-level shutdown applications and analog monitoring applica- tions such as power supply sequencing. because an lt1339 controlled converter is a power transfer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourcing capabilities of that supply, causing the system to lock up in an undervoltage state. input supply start-up protection can be achieved by enabling the run/shdn pin using a resistor divider from the input supply to ground. setting the divider output to 1.25v when that supply is almost fully enabled prevents the lt1339 regu- lator from drawing large currents until the input supply is able to provide the required power. if additional hysteresis is desired for the enable function, an external feedback resistor can be used from the lt1339 regulator output. if connection to the regulator output is not desired, the 5v ref internal supply pin can be used. figure 3 shows a resistor connection on a 48v to 5v converter that yields a 40v v in start-up threshold for regulator enable and also provides about 10% input referred hysteresis. the shutdown function can be disabled by connecting the run/shdn pin to the 12v in rail. this pin is internally clamped to 2.5v through a 20k series input resistance and will therefore draw about 0.5ma when tied directly to 12v. this additional current can be minimized by making the connection through an external resistor (100k is typically used). operation with split supplies and supply sequencing n-channel power mosfets can parasitically turn them- selves on due to leakage currents or capacitive coupling onto the mosfet gate. in shutdown, this is prevented by active pull-down clamps on the tg and bg driver outputs of the lt1339. these clamps are active when 12v in > 0.7v. the 12v in power supply for the lt1339 is usually derived from the converter input supply; however, these supplies can be independent. if these supplies are independent and 10k 300k v out 5v 1339 ?f03 5v ref lt1339 2 run/shdn 13 390k v in 48v option 2 option 1 figure 3. input supply sequencing programming
12 lt1339 sn1339 1339fas applicatio n s i n for m atio n wu u u the converter input supply is enabled with no voltage on the lt1339 12v in pin, the lt1339 driver output clamps will not be activated. to prevent turn-on, an external current path must be used to bleed off charge on the switch mosfet gates. high value bleed resistors (50k to 250k) should be connected between the tg and sw pins and between bg and pgnd. this provides discharge paths for the switch mosfet gates, preventing parasitic turn-on and damage to the mosfets. inductor selection the inductor for an lt1339 converter is selected based on output power, operating frequency and efficiency require- ments. generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor ( d i). for a buck converter, the minimum inductor value for a desired maximum operating ripple current can be deter- mined using the following relation: l vvv if v min out in out oin = () - () ()()( ) d where f o = operating frequency. given an inductor value (l), the peak inductor current is the sum of the average inductor current (i avg )and half the inductor ripple current ( d i), or: ii vvv lf v pk avg out in out oin =+ () - () ()()( )( ) 2 the inductor core type is determined by peak current and efficiency requirements. the inductor core must with- stand peak current without saturating, and series winding resistance and core losses should be kept as small as is practical to maximize conversion efficiency. the lt1339 peak current limit threshold is 40% greater than the average current limit threshold. slope compensation effects reduce this margin as duty cycle increases. this margin must be maintained to prevent peak current limit from corrupting the programmed value for average current limit. programming the peak ripple current to less than 15% of the desired average current limit value will assure porper operation of the average current limit feature through 90% duty cycle (see slope compensation section). oscillator synchronization the lt1339 oscillator generates a modified sawtooth waveform at the c t pin between low and high thresholds of about 0.8v (vl) and 2.5v (vh) respectively. the oscillator can be synchronized by driving a ttl level pulse into the sync pin. this inputs to a one-shot circuit that reduces the oscillator high threshold to 2v for about 200ns. the sync input signal should have minimum high/low times of 3 1 m s. 0.8v 1339 f04 2v 2.5v (vl) sync v ct (vh) free run synchronized figure 4. free run and synchronized oscillator waveforms (at c t pin) slope compensation current mode switching regulators that operate with a duty cycle greater than 50% and have continuous inductor current can exhibit duty cycle instability. while a regulator will not be damaged and may even continue to function acceptably during this type of subharmonic oscillation, an irritating high-pitched squeal is usually produced. the criterion for current mode duty cycle instability is met when the increasing slope of the inductor ripple current is less than the decreasing slope, which is the case at duty cycles greater than 50%. this condition is illustrated in figure 5a. the inductor ripple current starts at i 1 , at the beginning of each oscillator switch cycle. current increases at a rate s1 until the current reaches the control trip level i 2 . the controller servo loop then disables the main switch (and enables the synchronous switch) and inductor current begins to decrease at a rate s2. if the current switch point (i 2 ) is perturbed slightly and increased by d i, the cycle time ends such that the mini- mum current point is increased by a factor of (1 + s2/s1) to start the next cycle. on each successive cycle, this error is multiplied by a factor of s2/s1. therefore, if s2/s1 is 3 1, the system is unstable.
13 lt1339 sn1339 1339fas applicatio n s i n for m atio n wu u u subharmonic oscillations can be eliminated by augment- ing the increasing ripple current slope (s1) in the control loop. this is accomplished by adding an artificial ramp on the inductor current waveform internal to the ic (with a slope s x ) as shown in figure 5b. if the sum of the slopes s1 + s x is greater than s2, the condition for subharmonic oscillation no longer exists. for a buck converter, the required additional current wave- form slope, or slope compensation, follows the relation: s v l dc x in 3 ? ? ? ? - () 21 for duty cycles less than 50% (dc < 0.5), s x is negative and is not required. for duty cycles greater than 50%, s x takes on values dependent on s1 and duty cycle. this leads to a minimum inductance requirement for a given v in and duty cycle of: l v s dc min in x = ? ? ? ? - () 21 the lt1339 contains an internal s x slope compensation ramp that has an equivalent current referred value of: 0.084 f r o sense ? ? ? ? amp/s where f o is oscillator frequency. this yields a minimum inductance requirement of: l vr dc f min in sense o 3 ()( ) - () ()() 21 0 084 . a down side of slope compensation is that, since the ic servo loop senses an increase in perceived inductor current, the internal current limit functions are affected such that the maximum current capability of a regulator is reduced by the same amount as the effective current referred slope com- pensation. the lt1339, however, uses a current limit scheme that is independent of slope compensation effects (average current limit). this provides operation at any duty cycle with no reduction in current sourcing capability, provided ripple current peak amplitude is less than 15% of the current limit value. for example, if the supply is set up to current limit at 10a, as long as the peak inductor current is less than 11.5a, duty cycles up to 90% can be achieved without compromising the average current limit value. if an inductor smaller than the minimum required for internal slope compensation (calculated above as l min ) is desired, additional slope compensation is required. the lt1339 provides this capability through the sl/adj pin. this feature is implemented by referencing this pin via a resistor divider from the 5v ref pin to ground. the addi- tional slope compensation will be affected at the point in the oscillator waveform (at pin ct) corresponding to the voltage set by the resistor divider. additional slope com- pensation can be calculated using the relation: s f rr xadd o eq sense = ()() ()( ) 2500 amp/s where r eq is the effective resistance of the resistor divider. actual compensation will be somewhat greater due to in- ternal curvature correction circuitry that imposes an expo- nential increase in the slope compensation waveform, oscillator period time 0 0 ab ? i t1 i 2 i 1 s1 s1 s2 s2 s1 + s x 1339 ?f05 figure 5. inductor current at dc > 50% and slope compensation adjusted signal duty cycle (dc) 0 ? peak/ ? avg 0.4 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 lt1339 ?f06 0.2 0.6 0.1 0.5 0.3 0.7 0.8 0.9 figure 6. maximum ripple current (normalized) vs duty cycle for average current limit
14 lt1339 sn1339 1339fas applicatio n s i n for m atio n wu u u selection criteria for the power mosfets include the on resistance (r ds(on) ), reverse transfer capacitance (c rss ), maximum drain-source voltage (v dss ) and maximum output current. the power fets selected must have a maximum operating v dss exceeding the maximum v in . v gs voltage maximum must exceed the 12v in supply voltage. once voltage requirements have been determined, r ds(on) can be selected based on allowable power dissipation and required output current. in an lt1339 buck converter, the average inductor current is equal to the dc load current. the average currents through the main and synchronous switches are: i main = (i load )(dc) i sync = (i load )(1 C dc) the r ds(on) required for a given conduction loss can be calculated using the relation: p loss = (i switch ) 2 (r ds(on) ) further increasing the effective compensation slope up to 20% for a given setting. design example: v in = 20v v out = 15v (dc = 0.75) r sense = 0.01 w f o = 100khz l = 5 m h the minimum inductor usable with no additional slope compensation is: l v h min 3 () w () - () ()( ) =m 20 0 01 1 5 1 0 084 100000 11 9 .. . . since l = 5 m h is less than l min , additional slope compen- sation is necessary. the total slope compensation required is: s v h x 3 m ? ? ? ? - () = () ? ? ? 20 5 15 1 2 10 6 . amp/s subtracting the internally generated slope compensation and solving for the required effective resistance at sl/adj yields: r f rf k eq o sense o ()() () ? ? ? () - ()() = 2500 2 10 0 084 21 5 6 . . setting the resistor divider reference voltage at 2v assures that the additional compensation waveform will be enabled at 75% duty cycle. as shown in figure 7a, using r sl1 = 45k and r sl2 = 30k sets the desired reference voltage and has a r eq of 18k, which meets both design requirements. figure 7b shows the slope compensation effective waveforms both with and without the sl/adj external resistors. power mosfet and catch diode selection external n-channel mosfet switches are used with the lt1339. the positive gate-source drive voltage of the lt1339 for both switches is roughly equivalent to the 12v in supply voltage, so standard threshold mosfets can be used. r sl2 30k r sl1 45k 1339 ?f07a 5v ref lt1339 2 sl/adj 4 figure 7a. external slope compensation resistors figure 7b. slope compensation waveforms (0.084 + 0.139)(f o ) r sense (0.084)(f o ) r sense 2.5v 2v 0.8v dc = 0.75 1339 ?f07b
15 lt1339 sn1339 1339fas applicatio n s i n for m atio n wu u u 2000 hours (three months) lifetime; it is advisable to derate either the esr or temperature rating of the capaci- tor for increased mtbf of the regulator. the output capacitor in a buck converter generally has much less ripple current than the input capacitor. peak-to- peak ripple current is equal to that in the inductor ( d i l ), typically a fraction of the load current. c out is selected to reduce output voltage ripple to a desirable value given an expected output ripple current. output ripple ( d v out ) is approximated by: d v out ? d i l {esr + [(4)(f o ) ? c out ] C1 } where f o = operating frequency. efficiency considerations and heat dissipation high output power applications have inherent concerns regarding power dissipation in converter components. although high efficiencies are achieved using the lt1339, the power dissipated in the converter climbs to relatively high values when the load draws large amounts of power. even at 90% efficiency, an application that provides 500w to the load has conversion loss of 55w. i 2 r dissipation through the switches, sense resistor and inductor series resistance create substantial losses under high currents. generally, the dominant i 2 r loss is evident in the fet switches. loss in each switch is proportional to the conduction time of that switch. for example, in a 48v to 5v converter the synchronous fet conducts load cur- rent for almost 90% of the cycle time and thus, requires greater consideration for dissipating i 2 r power. gate charge/discharge current creates additional current drain on the 12v supply. if powered from a high voltage input through a linear regulator, the losses in that regula- tor device can become significant. a supply solution bootstrapped from the output would draw current from a lower voltage source and reduce this loss component. transition losses are significant in the topside switch fet when high v in voltages are used. transition losses can be estimated as: p tloss ? 2(v in ) 2 (i max )(c rss )(f o ) since the conduction time in the main switch of a 48v to 5v converter is small, the i 2 r loss in the main switch fet in high voltage applications (v in > 20v), the topside switch is required to slew very large voltages. as v in increases, transition losses increase through a square relation, until it becomes the dominant power loss term in the main switch. this transition loss takes the form: p tr ? (k)(v in ) 2 (i max )(c rss )(f o ) where k is a constant inversely related to the gate drive current, approximated by k = 2 in lt1339 applications. the maximum power loss terms for the switches are thus: p main = (dc)(i max ) 2 (1 + d )(r ds(on) ) + 2(v in ) 2 (i max )(c rss )(f o ) p sync = (1 C dc)(i max ) 2 (1 + d )(r ds(on) ) the (1 + d ) term in the above relations is the temperature dependency of r ds(on) , typically given in the form of a normalized r ds(on) vs temperature curve in a mosfet data sheet. in some applications, parasitic fet capacitances couple the negative going switch node transient onto the bottom gate drive pin of the lt1339, causing a negative voltage in excess of the absolute maximum rating to be imposed on that pin. connection of a catch schottky (rated to about 1a is typically sufficient) from this pin to ground will eliminate this effect. c in and c out supply decoupling capacitor selection the large currents typical of lt1339 applications require special consideration for the converter input and output supply decoupling capacitors. under normal steady state operation, the source current of the main switch mosfet is a square wave of duty cycle v out /v in . most of this current is provided by the input bypass capacitor. to prevent large input voltage transients and avoid bypass capacitor heating, a low esr input capacitor sized for the maximum rms current must be used. this maximum capacitor rms current follows the relation: i ivvv v rms max out in out in ? () ( ) () / 12 which peaks at a 50% duty cycle, when i rms = i max /2. capacitor ripple current ratings are often based on only
16 lt1339 sn1339 1339fas applicatio n s i n for m atio n wu u u is also small. however, since the fet gate must switch up past the 48v input voltage, transition loss can become a significant factor. in such a case, it is often prudent to take the increased i 2 r loss of a smaller fet in order to reduce c rss and thus, the associated transition losses. gate drive buffers the lt1339 is designed to drive relatively large capacitive loads. however, in certain applications, efficiency im- provements can be realized by adding an external buffer stage to drive the gates of the fet switches. when the switch gates load the driver outputs such that rise/fall times exceed about 100ns, buffers can sometimes result in efficiency gains. buffers also reduce the effect of back injection into the bottom side driver output due to coupling of switch node transitions through the switch fet c miller . paying the physicists in high power synchronous buck configurations, certain physical characteristics of the external mosfet switches can impact conversion efficiency. as the input voltage approaches about 30v, the bottom mosfets will begin to exhibit phantom turn-on. this phenomenon is caused by coupling of the instantaneous voltage step on the bottom side switch drain through c miller to the device gate, yielding internal localized gate-source voltages above the turn-on threshold of the fet. this generates a shoot- through blip that ultimately eats away at efficiency num- bers. in figure 8 a negative prebias circuit is added to the bottom side gate. the addition of this ~ 3v of negative offset to the bottom gate drive provides additional off- state voltage range to prevent phantom turn-on. fetkey is a trademark of international rectifier corporation. ts 12v in bg pgnd lt1339 ztx649 ztx749 d1n914 1339 f08 10k 1 f 3.3v figure 8. bottom side driver negative prebias circuit this type of prebias circuit is used in the 48v to 5v, 50a converter pictured in the typical applications section. as currents increase beyond the 10a to 15a range, the bottom side fet body diode experiences hard turn-on during switch dead time due to local current loop induc- tance preventing the timely transfer of charge to the schottky catch diode. the charge current required to commutate this body diode creates a high dv/dt schottky avalanche when the diode charge is finally exhausted (due to an effective inductor current discontinuity at the moment the body diode no longer requires charge). this generates an increased turn-on power burst in the topside switch, causing additional conversion efficiency loss. this effect of this parasitic inductance can be reduced by using fetkey tm mosfets, which have parallel catch schottky diodes internal to their packages. fetkey mosfets are not available for high voltages, so as input voltage contin- ues to increase, they can no longer be used. because this necessitates the use of discrete fets and schottkys, interdigitation of a number of smaller devices is required to minimize parasitic inductances. this technique is also used in the 48v to 5v, 50a converter shown in the typical applications section. optimizing transient responsecompensation component values the dominant compensation point for an lt1339 con- verter is the v c pin (pin 7), or error amplifier output. this pin is connected to a series rc network, r vc and c vc . the infinite permutations of input/output filtering, capacitor esr, input voltage, load current, etc. make for an empirical method of optimizing loop response for a specific set of conditions. loop response can be observed by injecting a step change in load current. this can be achieved by using a switchable load. with the load switching, the transient response of the output voltage can be observed with an oscilloscope. iterating through rc combinations will yield optimized response. refer to ltc application note 19 in 1990 linear applications handbook, volume 1 for more information.
17 lt1339 sn1339 1339fas typical applicatio n s u 6 7 10 20 19 18 11 12 16 14 13 9 17 u1 lt1339 12v 15 8 c14 3300pf c12 100pf r9 12k r10 10k 1% r8 301k 1% r6, 100 r7 100 d5 bat54 + + + + + 1339 ta05 t1 13:2 c1: sanyo 63mv680gx c2: wima smd4036/1.5/63/20/tr c6: kemet t510x477m006as (x8) l1: gowanda 50-318 t1: gowanda 50-319 l1 1.5 h r5 2.49k 1% ss v c v ref v boost tg ts sense + sense bg phase run/shdn v fb sgnd 12v in pgnd c15 0.1 f c10 0.1 f c9 1800pf 5% npo c11 0.1 f d2 murs120 d4 mbr0530t1 sync 1 2 4 3 5 5v ref sl/adj ct i avg 8 7 6 5 v cc1 out1 v cc2 out2 in1 gnd1 in2 gnd2 1 2 3 4 u2, ltc1693-2 8 7 6 5 v cc1 out1 v cc2 out2 in1 gnd1 in2 gnd2 1 2 3 4 u3, ltc1693-2 + c7 1 f + c13 1 f + c5 1 f + c1 680 f 63v q1 mtd20n06hd d3 murs120 q3 mtd20n06hd 4 3 21 d1 murs120 + c8 1 f r1 0.04 8 7 6 5 4 q4 si4420 x2 q2 si4420 x2 v out 1,8v 20a 3 21 8 7 6 5 + c3 4700pf 25v r2 5.1 + c6 470 f 6.3v x8 + c4 0.1 f r3 549 1% r4 1.24k 1% v in 48v + c2 1.5 f 63v + 48v to 1.8v 2-transistor synchronous forward converter
18 lt1339 sn1339 1339fas typical applicatio n s u w2 t2 w1 w3 6 5 7 2 v cc2 out2 out1 gnd1 v cc1 in2 in1 gnd2 8 3 1 4 ltc1693-1 6 5 7 2 v cc2 out2 out1 gnd1 gnd2 in2 v cc1 in1 4 3 8 1 ltc1693-1 v + comp rtop gnd-f gnd-s rmid 657 324 t2 t1 w4 t2 4.7k 470 470 bat54 bat54 w5 w1 w4 sud30n04-10 sud30n04-10 irf1310ns 1nf sec hv 10 10 4.8 h panasonic etqp af4r8h 1nf c3 330 f 6.3v c4 330 f 6.3v c5 330 f 6.3v 10 4.7nf 4.7nf 47 0.1 f t2 w3 4.7k + + + ? out +v out ? out +v out output 5v/10a c3, c4, c5: sanyo os-con 1 f fzt600 4.7 f 25v 0.47 f 50v 2k 3.1v mmft3904 10 bas21 sec hv lt1431cs8 ref coll 18 1k 470 100k 3.01k 1% 4.42k 1% 9.31k 1% 0.01 f +v out 0.22 f 1k ? out short jp1 for 5v out v boost tg ts sense + sense 12v in run/shdn phase bg v fb sync 5v ref ct sl/adj i avg v ref sgnd pgnd ss v c lt1339 + 100k +v in 13k 100k 2.4k 4.53k 0.1 f 1 f 2.2nf 2.2nf 0.1 f 4.7nf 68 f 20v avx tspe 3.9k 17 13 14 1 20 19 18 11 12 2 3 4 5 10 8 15 6 7 16 9 mmbd914lt1 3.3 1 f cny17-3 p p 36k bas21 bas21 bas21 p jp2 jp3 5v out short jp3, open jp2 3.3v out , short jp2, open jp3 coilcraft do1608-105 t1 10k 10 2.2 f 0.025 1/2w 470 10 fmmt718 fmmt718 p irf1310ns murs120 murs120 12v 2.2 f mmbd914lt1 470 bat54 w2 c1 1.2 f 100v cer c2 1.2 f 100v cer +v in p ? in +v in +v in w3, 10t 32awg, w4, 10t 32awg w5, 10t 2 x 26awg w4, 7t 6 x 26awg w1, 18t bifilar 31awg w3, 6t bifilar 31awg w1, 10t 2 x 26awg w1, 10t 32awg, w2, 15t 32awg 2mil poly film 2mil poly film output current 012345678910 efficiency 95 90 85 36v in 48v in 72v in t1 philips efd20-3f3 core l p = 720 h (ai = 1800) t2 er11/5 core ai = 960 h 1339 ta06 input 36v to 75v 48v to 5v isolated synchronous forward dc/dc converter
19 lt1339 sn1339 1339fas information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. sw package 20-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) s20 (wide) 0396 note 1 0.496 ?0.512* (12.598 ?13.005) 20 19 18 17 16 15 14 13 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 11 12 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** package descriptio n u dimensions in inches (millimeters) unless otherwise noted. n package 20-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n20 1197 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () 0.255 0.015* (6.477 0.381) 1.040* (26.416) max 12 3 4 5 6 7 8 910 19 11 12 13 14 16 15 17 18 20 *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) typical applicatio n s u 5v to 28v dc/dc synchronous boost converter limits input current at 60a (dc) v boost tg ts 12v in bg pgnd phase run/shdn sense sense + 12v c 12vin 47 f irf3205 2 irf3205 4 l1 40 h v in 5v at 60a r fb2 , 1.2k r fb1 , 27k sync 5v ref ct sl/adj i avg ss v c sgnd v fb v ref lt1339 + cbst 1 f + c in 2200 f 6.3v 4 + c 12l 1 f + r r1 100k r ct 10k c ct 2200pf c avg 2200pf c ss , 10 f c vc , 1500pf r vc , 7.5k c ref , 0.1 f 1339 ta04 l1 = 12t 4x12 on 77439-a7 c 5vref 1 f dbst mbr0530 q1 fmmt619 q2 fmmt720 q3 fmmt619 q4 fmmt720 d2 mbr0520 d1 ir30bq060 8 r ss2 , 100 r ss1 100 r s 0.002 c out 2200 f 35v 6 + v out 28v + +
20 lt1339 sn1339 1339fas ? linear technology corporation 1997 lt/tp 0299 2k rev a ? printed in the usa typical applicatio n u 48v to 5v 50a dc/dc converter with input supply start-up protection related parts part number description comments lt1158 half-bridge n-channel mosfet driver current limit protection, 100% of duty cycle lt1160 half-bridge n-channel mosfet driver up to 60v input supply, no shoot-through lt1162 dual half-bridge n-channel mosfet driver v in to 60v, good for full-bridge applications lt1336 half-bridge n-channel mosfet driver smooth operation at high duty cycle (95% to 100%) ltc ? 1530 high power step-down switching regulator controller excellent for 5v to 3.xv up to 50a ltc1435a high efficiency, low noise current mode step-down dc/dc converter drives synchronous n-channel mosfets ltc1438 dual high efficiency, low noise synchronous step-down controller tight 1% reference lt1680 high power dc/dc current mode step-up controller high side current sense, up to 60v input sync 5v ref ct sl/adj i avg ss v c sgnd v fb v ref v boost tg ts 12v in bg pgnd phase run/shdn sense sense + 12v c 12vin 47 f irfz44 2 irfz44 4 l1 40 h v out 5v at 50a r fb2 1k r fb1 3k lt1339 + cbst 1 f + c out 2200 f 6.3v, 4 + r r1 22k r r3 51k r ct 10k + c ct 2200pf c avg , 2200pf c ss , 10 f c vc , 2200pf r vc , 4.7k c ref 0.1 f 1339 ta01 d1 = ir30bq060 8 q1, q3 = fmmt619; q2, q4 = fmmt720 l1 = kool m , 12t 4x12 on 77439-a7 kool m is a registered trademark of magnetics, inc. c 5vref 1 f dbst in5819 q1 q2 q3 q4 d2 mbr0520 d4 in914 d1 r s 0.002 c in 1500 f 63v, 6 + v in 48v r r2 1.2k c bg , 1 f d3 mmsz4684 r bg 10k 50ma 48v to 5v efficiency output current (amps) 0 efficiency (%) 100 95 90 85 80 75 70 65 60 55 50 40 lt1339 ?ta02 10 20 30 50 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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